Astek has delivered a diverse set of designs ranging from Ethernet, Software Defined Radio, custom embedded processors, Image Processing, storage and interface. We support design on Xilinx, Altera and Lattice, on single FPGAs or proprietary platforms. We stand ready to meet your needs!
FPGA DESIGNS
Ethernet DMA Controller
Features: 25MB/second transfer rate between external FIFOs and processor bus; simultaneous input/output operation; controls multiple external devices on processor bus; design converted from original gate-level schematics to synthesizable RTL for FPGA implementation; all external pinouts/timing unchanged; ASIC replaced with Xilinx Spartan-II FPGA.
Custom DSP Embedded Controller
Features: 100 Mhz, 16 bit fixed point pipelined dual harvard architecture with dual MACs. We first supplied a SystemC based simulation model for multiple customers. We refined, improved model till both our client and thier contractors were satisfied, then used that model to verify the RTL as well as provide a basis for Intruction Set Simulator. Design was produced in both FPGA and ASIC format.
ICE V6M Customization
Features: Implemented a Software Defined Radio function including digital modulators, demodulators, FEC and signal conditioning on the Inovative Computer Engineering (ICE) V6M platform. Deliveries included RTL, SystemVerilog based verification environment, JAVA based system interface. We supported product thru client lab debug, system integration and validation. At clients request, we also supported Xmidas integration.
Custom DSP Embedded Controller
Features: 100 Mhz, 16 bit fixed point pipelined dual harvard architecture with dual MACs. We first supplied a SystemC based simulation model for multiple customers. We refined, improved model till both our client and thier contractors were satisfied, then used that model to verify the RTL as well as provide a basis for Intruction Set Simulator. Design was produced in both FPGA and ASIC format.
Custom Digital Demodulator
Features: Design supported advanced protocols such as DVBS-2.We implemented fixed point design using clients MatLab float point models using Altera Stratix4 based proprietary platform. Individual blocks include DDC, carrier-phase reconstruction, channel equalization, AGC, adaptive equalization, soft decision and hard decision decoding, FEC decoding. Design was supported thru clients lab debug, system validation and was fielded as a platform capability.
Programmable Timer Chip
Features: RISC processor interface; multiple cascadable internal counters; programmable internal timer; design converted from original gate-level schematics to synthesizable RTL for FPGA implementation; all external pinouts/timing unchanged; ASIC replaced with Xilinx Virtex FPGA.
TELECOM - SONET/SDH OC-3/12
Features: Section, Line, and Path terminating interfaces; Astek has worked on Regenerators and Multiplexers, designing Framers, Pointer Processors, and overhead termination; single mode fiber interface (PHY) for DC-3 and DC-12.
TELECOM - ATM
Features: ARM SAR, AAL-5 re-assembly, AAL-2 re-assembly; Astek has experience with ATM AAL-5 SAR and AAL-2 SAR design and test.
FIR/IIR DSP Test Platform
Implements multiple FIR/IIR DSP filter stages; 8-bit datapath; externally programmable filter coefficients; verifies proof of concept for new DSP algorithms; implemented in Xilinx Virtex FPGA.
Voice-over-IP Test Chip
Implements transmit and receive operations; controls data flow between transceivers, SDRAM, and PCI interfaces; 60 input channels; designed in VHDL; implemented in Xilinx 4000 series FPGA.